In a radio frequency system, the signal to be transmitted over the radio channel is often modulated using a selected modulation method and the modulated signal is then converted to a higher frequency so as to be transmitted at a designated band. For example, in the North America, the conventional television signal is modulated using VSB modulation and the modulated television signal is up converted to VHF or UHF band for transmission. On the receiver side, the received radio frequency (RF) signal is down converted to a zero-IF, low-IF or regular IF signal for further processing. The use of down conversion in a receiver system converts the high frequency RF signal down to a lower frequency zero-IF, low-IF or IF signal. As is well known in the field of electronic circuit, a high performance circuit, such as an amplifier or a filter, is harder to implement in a higher frequency than in a lower frequency. The use of down conversion will ease the implementation of receiver circuit. Another great benefit of down conversion is that the converted zero-IF, low-IF and IF signals are more suited for digital processing where the receiver may take advantage of flexibility and programmability offered by digital signal processing. Therefore, up conversion has been widely used in a transmitter and down conversion has been widely used in a receiver. In either case, there is a need to provide a local oscillation signal to mix with the incoming signal for up conversion or down conversion.
Furthermore, the signal to be transmitted or the input signal received by a receiver may cover a wide range of frequencies. The LO circuit will have to provide LO signals over a wide range of frequencies. In order to reduce the wide tuning range, it has been described in the literature that an LO system may use higher VCO frequency followed by divide-by-4 and divide-by-6 dividers to generate differential LO signals for 1 and Q channels. This method can reduce the tuning range of the VCO from 100% to 50%. However, the working frequency range becomes much higher and the higher VCO frequency implies higher power consumption.
The invention disclosed in the U.S. Provisional Patent Application, No. 61/362,686, describes a high order harmonic mixing system which not only avoids the need for much higher LO frequency, but also substantially suppresses the first order and other higher order harmonics to alleviate the potential interference problem. Consequently, lower power consumption and high system performance in terms of signal-to-noise ratio (SNR) are achieved. According to the system disclosed in U.S. Provisional Patent Application, No. 61/362,686, a harmonic rejection mixer (HRM) is used to reject the interferences associated with 3rd- and 5th-order harmonic frequency. The interference signal will be converted to an IF signal if a traditional mixer is used. However, the high-order harmonic mixing system will convert the interference signal to a frequency outside the IF frequency region and consequently rejects the interference signal. In one example, the system requires LO signals with 0°, 45°, 90°, and 135° phase shifts respectively. Furthermore, the system also requires LO signals having phase shifts of 0°, 60° and 120°.
There are several circuits with different structure to generate the required clocks having the above prescribed phase shifts. For example, the LO signals with 0°, 45°, 90°, and 135° phase shifts may be generated by a circuit comprising two-stage dividers. The first stage contains a single divide-by-2 divider and the second stage contains a pair of parallelly connected divide-by-2 dividers coupled to the output of the first stage divider, and the first stage divider is driven by a differential clock having a frequency at four times the LO frequency. However, such implementation will result in phase uncertainty, which is a critical problem for the harmonic rejection mixer (HRM). A divide-by-4 divider using a differential clock will be able to provide the required clocks with the above prescribed phase shifts. However, some applications only need a divide-by-2 divider. For example, a divide-by-6 divider may be implemented as a divide-by-3 divider followed by a divide-by-2 divider. The use of a divide-by-4 divider in such case would unnecessarily increase the system cost. Therefore, it is much desired to develop systems and methods that can reliably and correctly generate a family of clocks with prescribed phase shifts.